Shift register unit, signal generation unit circuit, driving method and display device

A signal generation circuit comprising a plurality of stages of signal generation unit circuits, wherein any one of the plurality of stages of signal generation unit circuits comprises a signal generation circuit and an output control circuit, wherein,

• the signal generation circuit is connected to an (N-1)th stage of first carry signal terminal, a first clock signal terminal, a second clock signal terminal, a first signal output terminal, a first voltage terminal and a second voltage terminal, is configured to generate an N-th stage of first carry signal according to an (N-1)th stage of first carry signal, a first clock signal, a second clock signal, a first voltage signal and a second voltage signal, control a potential of a second node,
• the first clock signal terminal is used to provide the first clock signal, the second clock signal terminal is used to provide the second clock signal;
• the (N-1)th stage of first carry signal terminal is used to provide the (N-1)th stage of first carry signal;
• the first voltage terminal is used to provide the first voltage signal, and the second voltage terminal is used to provide the second voltage signal;
• an N-th stage of signal generation circuit is electrically connected to
• the (N-1)th stage of first carry signal terminal,
• an N-th stage of first carry signal terminal,
• an N-th stage of first signal output terminal,
• an (N-1)th stage of second carry signal terminal and
• N is a positive integer.