Input-output module, frequency conversion module, control methods and chip

A frequency conversion module, comprising:

• a parser and a plurality of frequency multipliers, wherein each of the frequency multipliers is connected to the parser, respectively;
• the parser is configured to parse acquired data to be parsed to acquire a plurality of sets of frequency conversion data, each of which comprises an identifier of frequency multiplier and a frequency conversion value, and configured to send, based on the identifier of frequency multiplier in each set of the frequency conversion data, each set of the frequency conversion data to a corresponding frequency multiplier, respectively;
• and
• each of the frequency multipliers is configured to multiply an input frequency by a factor which is determined by the received frequency conversion value.

An input-output module having M input pins and N output pins, wherein the M input pins comprise a path pin, an instruction pin and a shift pin, and the input-output module comprises:

• a path switcher having an input terminal, a path terminal and N output terminals, a shift register having a shift terminal, N input terminals and N output terminals, and a flip-flop having N input terminals and N output terminals;
• wherein
• the input terminal of the path switcher is connected to the instruction pin, the path terminal of the path switcher is connected to the path pin, the N output terminals of the path switcher are connected to the N input terminals of the shift register in one to one correspondence, the path switcher is configured to transmit an enable signal provided by the path pin to one of the N output terminals of the path switcher which is indicated by a path switching signal provided by the instruction pin;
• the shift terminal of the shift register is connected to the shift pin, the N input terminals of the shift register are connected to the N output terminals of the path switcher in one-to-one correspondence, the N output terminals of the shift register are connected to the N input terminals of the flip-flop in one-to-one correspondence, the N input terminals of the shift register are in one-to-one correspondence with the N output terminals of the shift register, the shift register is configured to:
• receive at least one enable signal from at least one of the N input terminals of the shift register before a shift signal provided by the shift pin is received, and, send the at least one enable signal to at least one corresponding output terminal of the shift register when the shift signal provided by the shift pin is received;
• and
• the N output terminals of the flip-flop are connected to the N output pins in one-to-one correspondence, the N input terminals of the flip-flop are in one-to-one correspondence with the N output terminals of the flip-flop, and the flip-flop is configured to receive at least one enable signal from at least one of the N input terminals of the flip-flop, and flip an output level of at least one corresponding output terminal of the flip-flop.