US 2026/0267610 A1 · MULTIPLICATION AND ACCUMULATION (MAC) OPERATOR

Abstract

A multiplication-accumulation (MAC) includes a multiply-accumulate circuit configured to receive weight data and vector data, and to generate and output maximum exponent data and exponent data of multiply-accumulate data. The multiply-accumulate circuit includes a multiplication circuit that performs a multiplication operation on the weight data and the vector data to output sign data, modified exponent data, and mantissa data of each of multiplication data, a pre-processing circuit that separates each of the exponent data of the multiplication data to generate exponent upper data and exponent lower data, and performs exponent pre-processing using the exponent upper data and mantissa pre-processing using the exponent lower data to output maximum exponent upper data and pre-processed mantissa data, and an adder tree that adds the pre-processed mantissa data to generate and output mantissa data of the multiply-accumulate data.

Claims20

Dependent claims

A multiply-accumulate (MAC) operator comprising:

a multiply-accumulate circuit configured to receive weight data and vector data, and to generate and output maximum exponent data and exponent data of multiply-accumulate data,
wherein the multiply-accumulate circuit includes:
a multiplication circuit that performs a multiplication operation on the weight data and the vector data to output sign data, modified exponent data, and mantissa data of each of multiplication data;
a pre-processing circuit that separates each of the exponent data of the multiplication data to generate exponent upper data and exponent lower data, and performs exponent pre-processing using the exponent upper data and mantissa pre-processing using the exponent lower data to output maximum exponent upper data and pre-processed mantissa data;
and
an adder tree that adds the pre-processed mantissa data to generate and output mantissa data of the multiply-accumulate data.

3 more elements

A multiplication-addition (MAC) operator comprising:

a left multiplication addition circuit configured to receive left weight data and left vector data to generate and output left maximum exponent data and exponent data of left multiplication addition data;
and
a right multiplication addition circuit configured to receive right weight data and right vector data to generate and output right maximum exponent data and exponent data of right multiplication addition data,
wherein the left multiplication addition circuit includes:
a left multiplication circuit that performs a multiplication operation on the left weight data and the left vector data to output sign data, modified exponent data, and mantissa data of each of left multiplication data;
a left pre-processing circuit that separates each of the exponent of the left multiplication data to generate left exponent upper data and left exponent lower data and performs left exponent pre-processing using the left exponent upper data and left mantissa pre-processing using the left exponent lower data to output left maximum exponent upper data and left pre-processed mantissa data;
and
a left adder tree that adds the left pre-processed mantissa data to generate and output mantissa data of the left multiplication addition data, and
wherein the right multiplication addition circuit includes:
a right multiplication circuit that performs a multiplication operation on the right weight data and the right vector data to output sign data, modified exponent data, and mantissa data of each of right multiplication data;
a right pre-processing circuit that separates each of the exponent of the right multiplication data to generate right exponent upper data and right exponent lower data and performs right exponent pre-processing using the right exponent upper data and right mantissa pre-processing using the right exponent lower data to output right maximum exponent upper data and right pre-processed mantissa data;
and
a right adder tree that adds the right pre-processed mantissa data to generate and output mantissa data of the right multiplication addition data.

10 more elements

Dependencies are inferred from the claim text.

Multiplication and accumulation (mac) operator

Life of this patent

Multiplication and accumulation (mac) operator

Life of this patent

Abstract

Claims20