Optically interconnected network interface controller (nic)

Abstract

Described herein are systems that integrate a network interface controller (NIC) with a processing unit through co-packaging to improve bandwidth and latency while reducing power consumption. The NIC may be 3D stacked on top of a photonic interposer. A chip-to-chip interface between the NIC and the processing unit addresses bandwidth bottlenecks and latency associated with conventional PCIe-based approaches. The use of silicon photonics enables optical bandwidth that matches the bandwidth of the chip-to-chip interface while reducing power consumption compared to conventional approaches using active optical cables. The photonic interposer may include SRAM buffers for retransmission operations.

Dependencies are inferred from the claim text.