US 2026/0265047 A1 · WAFER LEVEL CHIP SCALE PACKAGING WITH SENSOR

Abstract

The present disclosure is directed to a package (e.g., a chip scale package, a wafer level chip scale package (WLCSP), or a package containing a sensor die) with a sensor die on a substrate (e.g., an application-specific integrated circuit die (ASIC), an integrated circuit, or some other type of die having active circuitry) and encased in a molding compound. The sensor die includes a sensing component that is aligned with a centrally located opening that extends through the substrate. The centrally located opening extends through the substrate at an inactive portion of the substrate. The centrally located opening exposes the sensing component of the sensor die to an external environment outside the package.

Claims20

Dependent claims

A method, comprising:

forming an opening extending through a substrate from a first surface of the substrate to a second surface of the substrate opposite to the first surface;
forming a solder ball on a first contact of a die;
forming a solder structure on a second contact of the die surrounding a sensing component of the die and the opening of the die;
and
forming a molding compound on sidewalls of the first die, on a surface of the substrate, and on a surface of the solder structure.

2 more elements

A method, comprising:

forming a plurality of first conductive layers on a plurality of pads along a second surface of a wafer opposite to a first surface of a wafer;
forming a first non-conductive layer on the second surface of the wafer and on the plurality of first conductive layers;
forming a first opening extending through the first non-conductive layer to the second surface of the wafer;
forming a plurality second openings extending through the first non-conductive layer to the plurality of first conductive layers;
coupling the first non-conductive layer to an adhesive on a support;
forming a plurality of electrical connections that extend into the first surface of the wafer to the plurality of pads;
forming a third opening aligned with the first opening by removing a respective portion of the wafer;
forming a plurality of second conductive layers on the plurality of electrical connections along the first surface of the wafer;
forming a second non-conductive layer on the plurality of second conductive layers and on the first surface of the wafer;
forming a plurality of fourth openings extending through the second non-conductive layer to the plurality of second conductive layers;
forming a plurality of first conductive portions on a plurality of contacts of a die;
forming a second conductive portion on a ring contact of the die, wherein the ring contact is spaced laterally inward from the plurality of contacts;
coupling the plurality of first conductive portions to the plurality of second conductive layers through the plurality of fourth openings and coupling the second conductive portion to the second non-conductive layer;
forming a molding compound on the second non-conductive layer, on the plurality of first conductive portions, on the second conductive portion, and on one or more sidewalls of the die.

11 more elements

A method, comprising:

forming a plurality of first conductive layers on a plurality of pads along a second surface of a wafer opposite to a first surface of a wafer;
forming a first non-conductive layer on the second surface of the wafer and on the plurality of first conductive layers;
forming a first opening extending through the first non-conductive layer to the second surface of the wafer;
forming a plurality second openings extending through the first non-conductive layer to the plurality of first conductive layers;
coupling the first non-conductive layer to an adhesive on a support;
forming a plurality of electrical connections that extend into the first surface of the wafer to the plurality of pads;
forming a third opening aligned with the first opening by removing a respective portion of the wafer;
forming a plurality of second conductive layers on the plurality of electrical connections along the first surface of the wafer;
forming a third conductive layer on one or more respective electrical connections of the plurality of electrical connections, wherein the third conductive layer is spaced laterally inward from the plurality of second conductive layers
forming a second non-conductive layer on the plurality of second conductive layers, on the third conductive layer, and on the first surface of the wafer;
forming a plurality of fourth openings extending through the second non-conductive layer to the plurality of second conductive layers;
forming a fifth opening extending through the second non-conductive layer to the third conductive layer;
forming a plurality of first conductive portions on a plurality of contacts of a die;
forming a second conductive portion on a ring contact of the die, wherein the ring contact is spaced laterally inward from the plurality of contacts;
coupling the plurality of first conductive portions to the plurality of second conductive layers through the plurality of fourth openings and coupling the second conductive portion to the third conductive layer through the fifth opening;
forming a molding compound on the second non-conductive layer, on the plurality of first conductive portions, on the second conductive portion, and on one or more sidewalls of the die.

13 more elements

Dependencies are inferred from the claim text.

Facts

Application

19/654,046Filed 21 Apr 2026

Priority

22 Jun 2020

Published

10 Sep 2026

Term ends

Not estimatedThe source records don’t support an estimate.

Classification6 codes

B81B 7/0061
Packages or encapsulation: suitable for fluid transfer from the MEMS out of the package or vice versa, e.g. transfer of liquid, gas, sound
B81C 1/00309
Processes for packaging MEMS devices: suitable for fluid transfer from the MEMS out of the package or vice versa, e.g. transfer of liquid, gas, sound
B81B 2201/0264
Sensors: pressure sensors
B81B 2207/07
Microstructural systems or auxiliary parts thereof: interconnects

Family

Application63/042,247Us provisional application · filed 22 Jun 2020

Application17/344,576Division · filed 10 Jun 2021

Application19/654,046Division

US 12,637,349 B2Related patent

US 2021/0395077 A1Published application

US 2026/0265047 A1This patent

From the US filing history. Foreign family members aren’t listed.

Wafer level chip scale packaging with sensor

Life of this patent

Wafer level chip scale packaging with sensor

Life of this patent

Abstract

Claims20