Chiplet system with reconfigurable logical memory macros

A memory chiplet, comprising:

• a plurality of physical memory macros, each comprising a plurality of memory cells and having a physical width and a physical depth;
• a physical interface configured to allow the memory chiplet to physically couple to and communicate with a compute chiplet;
• and
• a bus, coupled to each of the plurality of physical memory macros;
• wherein the plurality of physical memory macros may be reconfigured into one or more logical memory macros, each logical memory macro having a logical width and a logical depth which may be different to the physical width or the physical depth of the physical memory macros, and each logical memory macro including memory cells from one or more physical memory macros.

A method of establishing a logical memory macro in a memory chiplet, the method comprising:

• receiving, at a memory controller, a request from a compute chiplet for one or more memory macros, each having a width and a depth, in the memory chiplet;
• wherein the memory chiplet comprises a plurality of physical memory macros, each comprising a plurality of memory cells and having a physical width and a physical depth;
• the method further comprising:
• defining, at the memory controller, one or more logical memory macros in response to the request, the one or more logical memory macros having a logical width and a logical depth corresponding to the requested width and depth;
• wherein the logical width and logical depth may be different to the physical width or the physical depth of the physical memory macros, and each logical memory macro including memory cells from one or more physical memory macros.