US 2026/0259841 A1 · SYSTEM AND METHOD FOR ENABLING DATA TRANSFER

Abstract

The present disclosure relates to a system and a method for data transfer, and more specifically, to a system and a method for data transfer between a host NXP processor and a Radio Frequency System-on-Chip (RFSoC) using a PCIe bus. The method includes determining that data is set for transmission from a first processor to a second processor. The method includes copying the data to at least one memory address of the first processor based on the determination. The method includes triggering an inter-processor interrupt (IPI) over at least one channel of the second processor in response to the copying of the data. The method includes transmitting the data from the first processor to the second processor via the IPI.

Claims16

Dependent claims

A system (108) for data transfer, the system (108) comprising:

processors (202a, 202b);
and
a memory (204) operatively coupled with the processors (202a, 202b), wherein the memory (204) comprises processor-executable instructions, which on execution, cause a first processor (202a) of the processors (202a, 202b) to:
determine that data is set for transmission from the first processor (202a) to a second processor (202b) of the processors (202a, 202b);
copy the data to at least one memory address of the first processor (202a) based on the determination, wherein the at least one memory address of the first processor (202a) is directly mapped with at least one memory address of the second processor (202b);
in response to the copying of the data, trigger an inter-processor interrupt (IPI) over at least one channel of the second processor (202b);
and
transmit the data to the second processor (202b) via the IPI.

5 more elements

A method for data transfer, the method comprising:

determining, by a first processor (202a) associated with a system (108), that data is set for transmission to a second processor (202b);
copying, by the first processor (202a), the data to at least one memory address of the first processor (202a) based on the determination, wherein the at least one memory address of the first processor (202a) is directly mapped with at least one memory address of the second processor (202b);
triggering, by the first processor (202a), an inter-processor interrupt (IPI) over at least one channel of the second processor (202b) in response to copying the data;
and
transmitting, by the first processor (202a), the data to the second processor (202b) via the IPI.

2 more elements

Dependencies are inferred from the claim text.

System and method for enabling data transfer

Life of this patent

System and method for enabling data transfer

Life of this patent

Abstract

Claims16