US 2026/0255939 A1Published application

Sub-lithographically separated interconnect structures and methods of making the same

AssigneeSanDisk Technologies LLC

InventorsHiroshi NAKATSUJI, Kosuke TANAKA, Kiyokazu SHISHIDO, Eiichi FUJIKURA

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Abstract

Via cavities can be formed through a contact-level dielectric layer by performing an anisotropic via etch process that employs a hard mask layer containing hard mask openings as a via etch mask. Sacrificial spacer liners can be formed in peripheral regions of the via cavities. The hard mask layer can be patterned into at least one discrete hard mask plate. Integrated line-and-via cavities can be formed by performing an anisotropic line etch process that employs a combination of a patterned photoresist layer and the at least one discrete hard mask plate as a line etch mask. The patterned photoresist layer, the at least one discrete hard mask plate, and the sacrificial spacer liners can be removed. Metal interconnect structures can be formed within the integrated line-and-via cavities.

Claims20

Dependent claims

A method of forming a device structure, comprising:

forming a contact-level dielectric layer over a semiconductor device;
forming a hard mask layer containing hard mask openings over top surface of the contact-level dielectric layer;
forming via cavities through the contact-level dielectric layer by performing an anisotropic via etch process that employs a hard mask layer as a via etch mask;
forming sacrificial spacer liners in peripheral regions of the via cavities;
patterning the hard mask layer into at least one discrete hard mask plate;
forming integrated line-and-via cavities by performing an anisotropic line etch process that employs a combination of a patterned photoresist layer and the at least one discrete hard mask plate as a line etch mask, wherein the integrated line-and-via cavities include all volumes of the via cavities and volumes of line cavities that are formed by removal of upper portions of the contact-level dielectric layer by the anisotropic line etch process;
removing the patterned photoresist layer, the at least one discrete hard mask plate, and the sacrificial spacer liners, such that volumes of the integrated line-and-via cavities increase by volumes of the removed sacrificial spacer liners;
and
forming metal interconnect structures within the integrated line-and-via cavities.

6 more elements

A field effect transistor, comprising:

a semiconductor source region;
a semiconductor drain region;
a semiconductor channel region located between the semiconductor source region and the semiconductor drain region;
a gate dielectric layer located over the semiconductor channel region;
a gate electrode located over the gate dielectric layer;
a contact-level dielectric layer located over the gate electrode;
a drain integrated line-and-via structure embedded in the contact-level dielectric layer, and comprising a first via portion that contacts the semiconductor drain region and a first line portion overlying the first via portion;
and
a gate integrated line-and-via structure embedded in the contact-level dielectric layer, and comprising a second via portion that contacts the gate electrode and a second line portion overlying the second via portion,
wherein:
the first line portion comprises:
an elongated line portion that laterally extends along a first horizontal direction and is laterally offset from the first and second via portions along a second horizontal direction that is perpendicular to the first horizontal direction;
a stub portion that overlies the first via portion and having a first convex sidewall that extends substantially along the second horizontal direction;
and
a connection line portion that laterally extends along the second horizontal direction and connecting the stub portion and the elongated line portion;
the second line portion comprises a second convex sidewall that extends substantially along the second horizontal direction and faces the first convex sidewall;
and
the first and the second line portions are wider at their top than at their bottom.

15 more elements

Dependencies are inferred from the claim text.

Facts

Application: 19/065,306Filed 27 Feb 2025
Published: 27 Aug 2026
Term ends: Not estimatedThe source records don’t support an estimate.

Classification31 codes

H10W 20/056
Of conductive parts of the interconnections: by filling conductive material into holes, grooves or trenches
H10D 30/63
Insulated-gate field-effect transistors [IGFET]: vertical IGFETs
H10D 62/124
Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies: shapes, relative sizes or…
H10D 84/837
Of only insulated-gate FETs [IGFET]: comprising vertical IGFETs

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