Semiconductor device

A semiconductor device comprising:

• a substrate including a first surface and a second surface opposing one another;
• a first conductivity type semiconductor layer positioned on the first surface of the substrate and including a first element that is a semiconductor material and a second element that is different from the first element;
• a second conductivity type doped well region positioned within the first conductivity type semiconductor layer;
• a pillar layer positioned within the first conductivity type semiconductor layer and extending from the lower surface of the second conductivity type doped well region toward the substrate, the pillar layer having the second conductivity type and including the first element and the second element;
• a gate electrode positioned on the first conductivity type semiconductor layer;
• a gate insulating layer positioned between the first conductivity type semiconductor layer and the gate electrode;
• a source electrode positioned on the second conductivity type doped well region;
• and
• a drain electrode positioned on the second surface of the substrate,
• the pillar layer includes
• a first pillar pattern, and
• a second pillar pattern positioned between the first pillar pattern and the first conductivity semiconductor layer,
• wherein a content (at %) of the second element in the second pillar pattern is greater than a content (at %) of the second element in the first pillar pattern.

A semiconductor device comprising:

• a substrate including a first surface and a second surface opposing one another;
• a first conductivity type semiconductor layer including Si and C, positioned on the first surface of the substrate;
• a second conductivity type doped well region positioned within the first conductivity type semiconductor layer;
• a pillar layer positioned between the substrate and the second conductivity type doped well region, the pillar layer having the second conductivity type and including Si and C;
• a gate electrode positioned on the first conductivity type semiconductor layer;
• a gate insulating layer positioned between the first conductivity type semiconductor layer and the gate electrode;
• a source electrode positioned on the second conductivity type doped well region;
• and
• a drain electrode positioned on the second surface of the substrate,
• wherein the pillar layer includes:
• a first pillar pattern including Si at a first content (at %), and
• a second pillar pattern positioned between the first pillar pattern and the first conductivity type semiconductor layer, the second pillar pattern including Si at a second content (at %) smaller than the first content (at %),
• wherein the second content (at %) in the second pillar pattern is greater than or equal to the Si content (at %) of the first conductivity type semiconductor layer.