US 2026/0255469 A1 · BANDWIDTH ENHANCEMENT FOR DATA STORAGE DEVICES HAVING FLIP CHIP MEMORY DIES

Abstract

A data storage device includes a plurality of flip chip memory dies horizontally arranged on one or more surfaces of a PCB. The flip chip memory dies are coupled to a controller of the data storage device using variable impedance traces. A first portion of one variable impedance trace has a first impedance while a second portion of the variable impedance trace has a second impedance. The difference in impedance between the portions of the variable impedance trace is based, at least in part, on a configuration of one or more metal layers in the PCB. A resistor is placed between a first memory die of the plurality of memory dies and a second memory of the plurality of memory dies and is also used to increase an impedance of at least one of the portions of the variable impedance trace.

Claims20

Dependent claims

A semiconductor package, comprising:

a printed circuit board (PCB);
a controller mounted on the PCB;
a plurality of flip chip semiconductor dies mounted on the PCB;
a plurality of variable impedance traces electrically coupling the controller to the plurality of flip chip semiconductor dies;
and
a component positioned between a first flip chip semiconductor die in the plurality of flip chip semiconductor dies and a second flip chip semiconductor die in the plurality of flip chip semiconductor dies, the component increasing a resistance of at least a portion of at least one variable impedance trace of the plurality of variable impedance traces between the first flip chip semiconductor die and the second flip chip semiconductor die.

3 more elements

Dependencies are inferred from the claim text.

Bandwidth enhancement for data storage devices having flip chip memory dies

Life of this patent

Bandwidth enhancement for data storage devices having flip chip memory dies

Life of this patent

Abstract

Claims20