Clock stretch compensation for digital frequency-locked loop circuits

A method for compensating clock stretch in a processor, comprising:

• receiving voltage telemetry data indicating voltage droops in a supply voltage;
• detecting, based on the voltage telemetry data, a reduction in an operating frequency by a digital frequency-locked loop (DFLL) circuit having a stretch response slope;
• and
• increasing the supply voltage based on a difference between the operating frequency and a target frequency to counteract frequency reduction caused by the DFLL circuit's stretch response slope.

A clock stretch compensation (CSC) circuit for a processor, comprising:

• a first input configured to receive voltage telemetry data from a system management unit (SMU);
• a second input configured to receive frequency data indicating an operating frequency of a digital frequency-locked loop (DFLL) circuit;
• and
• control logic configured to:
• detect a reduction in the operating frequency caused by a stretch response of the DFLL circuit;
• and
• output a control signal to increase a supply voltage based on the detected reduction.