Memory circuit and method of forming the same

A memory circuit, comprising:

• a first memory cell comprising:
• a first fuse element on a front-side of a substrate opposite from a back-side of the substrate;
• a second fuse element on the front-side of the substrate, and being separated from the first fuse element in a first direction;
• a first selection transistor coupled to the first fuse element;
• a second selection transistor coupled to the second fuse element;
• and
• a first word line transistor coupled to at least the first selection transistor or the second selection transistor, and being on the front-side of the substrate,
• wherein one of the first fuse element or the second fuse element is programmed during a programming operation, and another of the first fuse element or the second fuse element fails to be programmed during the programming operation.

A method of fabricating a memory circuit, the method comprising:

• fabricating a first set of transistors in a front-side of a substrate, the first set of transistors including a first word line transistor and a first set of dummy transistors;
• fabricating a first set of vias on the front-side of the substrate, the first set of vias being electrically coupled to at least the first set of transistors;
• depositing a first conductive material on the front-side of the substrate on a first metal level thereby forming a first set of conductors, the first set of conductors being electrically coupled to at least the first set of transistors by the first set of vias, the first set of conductors including a first word line or a first cascode gate line, the first set of transistors being configured to receive a first word line signal on the first word line or a first cascode gate line signal on the first cascode gate line from the front-side;
• fabricating a first interconnect structure on the front-side of the substrate, the first interconnect structure being coupled to at least the first set of dummy transistors;
• fabricating a first set of fuse elements on the front-side of the substrate, the first set of fuse elements being coupled to the first set of transistors;
• performing thinning on a back-side of the substrate opposite from the front-side;
• fabricating a first set of back-side vias through the back-side of the substrate to the front-side of the substrate, the first set of back-side vias being electrically coupled to at least the first set of transistors;
• depositing a second conductive material on the back-side of the substrate on a second metal level thereby forming a second set of conductors, the second set of conductors being electrically coupled to the first set of transistors by the first set of back-side vias;
• and
• fabricating a second set of transistors on the back-side of the thinned substrate, the second set of transistors including a first selection transistor, the second set of transistors being electrically coupled to the second set of conductors.