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US 2026/0252497 A1Published application
Mitigating Row Hammer Attacks Through Memory Address Encryption
AssigneeApple Inc.
InventorJeff Gonion
Life of this patent
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Abstract
In an embodiment, a system employs encryption on memory addresses generated by a source circuit that generates memory transactions (e.g., a processor such as a central processing unit (CPU), a graphics processing unit (GPU), various embedded processors or microcontrollers; or a peripheral device. The encrypted memory address corresponds to the row that is activated for the memory transaction, instead of the memory address generated by the source circuit.
Claims20
An apparatus, comprising:
- a cryptographic key source circuit configured to generate, based on an initialization of the apparatus, a first set of cryptographic keys;
- one or more source circuits configured to initiate memory transactions, where a given memory transaction includes a memory address within a memory address space corresponding to a memory system;
- an encryption circuit configured to:
- obtain a particular one of the first set of cryptographic keys from the cryptographic key source circuit;
- receive the memory address of the given memory transaction;
- and encrypt, based on the particular cryptographic key, a portion of the memory address to form an encrypted memory address;
- and a memory circuit included in the memory system and configured to access, based on the encrypted memory address, data corresponding to the given memory transaction.
4 more elements
A method, comprising:
- performing, by a computer system, a boot of the computer system that includes an initialization of circuits of the computer system;
- generating, by the computer system based on the boot, a first set of cryptographic keys;
- initiating, by the computer system, a particular memory transaction that includes a particular memory address for a memory system in the computer system;
- encrypting, by the computer system using a particular one of the first set of cryptographic keys, the particular memory address to form an encrypted memory address;
- and selecting, by the computer system, a row of a memory device to access for the particular memory transaction using at least a portion of the encrypted memory address, wherein the selecting is performed without first decrypting the encrypted memory address.
2 more elements
A system, comprising:
- a memory system including a plurality of memory circuits that form a memory address space, wherein a given memory circuit is configured to access, based on an encrypted memory address included in a given memory transaction, a corresponding row of a plurality of rows in the given memory circuit;
- a plurality of source circuits configured to initiate memory transactions, wherein a particular one of the source circuits initiates the given memory transaction that includes an unencrypted memory address within the memory address space;
- one or more encryption circuits, wherein a given one of the encryption circuits is configured to:
- receive the unencrypted memory address of the given memory transaction;
- and encrypt the received memory address based on a particular cryptographic key to form the encrypted memory address;
- and a cryptographic key source circuit configured to, based on an initialization of the system and prior to an initiation of the given memory transaction, a first set of cryptographic keys, including the particular cryptographic key.
3 more elements
Dependencies are inferred from the claim text.