Apparatus and method for strided vector loads and stores with scalar progress tracking

A processor, comprising:

• decode circuitry to decode a progress tracking strided store instruction including fields to indicate a plurality of destination memory locations in which to store a corresponding plurality of source data elements, a vector register from which to read the corresponding plurality of source data elements, and a register to store a progress indication;
• execution circuitry to initiate execution of the progress tracking strided store instruction, the execution circuitry to:
• store one or more of the source data elements to corresponding destination memory locations;
• update the progress indication in accordance with the one or more source data elements successfully stored or a next source data element to be stored;
• and
• in response to an interruption of the execution of the strided store instruction, re-starting the execution of the strided store instruction from an execution point based on the progress indication.

A method, comprising:

• decoding a progress tracking strided load instruction including fields to indicate a destination vector register in which to load source data elements, memory locations of the source data elements, and a register to store a progress indication;
• initiating execution of the progress tracking strided load instruction;
• loading one or more of the source data elements to corresponding locations in the destination vector register;
• updating the progress indication in accordance with the one or more source data elements loaded or a next source data element to be loaded;
• and
• in response to an interruption of the execution of the progress tracking strided load instruction, re-starting the execution of the instruction from an execution point based on the progress indication.