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US 2026/0252160 A1Published application
Light sleep feature for cache memory
AssigneeQUALCOMM Incorporated
InventorsShyam SUNDAR, Xiao CHEN, Ramesh ARVAPALLI, Hoan Huu NGUYEN, Raghava Rao DENDULURI
Life of this patent
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Abstract
Certain aspects of the present disclosure provide techniques and apparatus for controlling a cache. According to certain aspects, at least one sub bank of a memory instance of the cache is placed in in a first low power state by 1) placing a bit line of at least one sub bank of the memory instance in a floating state, and 2) adjusting a core bias to reduce a level of a supply voltage rail to the sub bank from an active level to a retention level.
Claims20
A method for controlling a cache, comprising:
- placing at least one sub bank of a memory instance of the cache in a first low power state by 1) placing a bit line of at least one sub bank of the memory instance in a floating state, and 2) adjusting a core bias to reduce a level of a supply voltage rail to the sub bank from an active level to a retention level;
- and
- bringing the at least one sub bank out of the low power state prior to an access.
A processing system comprising:
- a cache;
- and
- memory control circuitry configured to
- place at least one sub bank of a memory instance of the cache in a first low power state by 1) placing a bit line of at least one sub bank of the memory instance in a floating state, and 2) adjusting a core bias to reduce a level of a supply voltage rail to the sub bank from an active level to a retention level;
- and
- bring the at least one sub bank out of the low power state prior to an access.
3 more elements
An apparatus, comprising:
- means for placing at least one sub bank of a memory instance of a cache in a first low power state by 1) placing a bit line of at least one sub bank of the memory instance in a floating state, and 2) adjusting a core bias to reduce a level of a supply voltage rail to the sub bank from an active level to a retention level;
- and
- means for bringing the at least one sub bank out of the low power state prior to an access.
Dependencies are inferred from the claim text.