Magnetic memory cell based on stt-assisted sot writing comprising an n-type transistor and a p-type transistor as select transistors, and mram memory

Abstract

An array of STT-assisted SOT-MRAM bit cells (CELL) each comprising a tri-layer element (TLE) including a ferromagnetic pinned layer, a ferromagnetic free layer, and a spacer interposed in-between, each of the STT-assisted SOT-MRAM bit cells (CELL) further including a SOT layer (SOT) adjacent to the ferromagnetic free layer and two select transistors (TrN, TrP), a first source line (SL) being, in the MRAM bit cell, connected to a second source line (SLB) through, in this order, a first one (TrN) of the two select transistors, the SOT layer (SOT), and a second one (TrP) of the two select transistors, the first one (TrN) and the second one (TrP) of the two select transistors being respectively an N-type transistor and a P-type transistor.

Dependencies are inferred from the claim text.