Memory cell array and memory device including thereof
AssigneeSamsung Electronics Co., Ltd.
InventorsYongjun Kim, Seunghan Woo, Hyun-Chul Yoon
Life of this patent
Estimating the term…
Abstract
A memory cell array may include a first memory cell including a first transistor structure and a first capacitor structure, a second memory cell including a second transistor structure and a second capacitor structure, and a first wordline contact connected to the first transistor structure and the second transistor structure, wherein the first capacitor structure is spaced apart from the first transistor structure in a first direction, and the second capacitor structure is spaced apart from the second transistor structure in a second direction different from the first direction.
Claims21
A memory cell array, comprising:
- a first memory cell including a first transistor structure and a first capacitor structure;
- a second memory cell including a second transistor structure and a second capacitor structure;
- and
- a first wordline contact electrically connected to the first transistor structure and the second transistor structure,
- wherein the first capacitor structure is spaced apart from the first transistor structure in a first direction, and the second capacitor structure is spaced apart from the second transistor structure in a second direction different from the first direction.
A memory cell array comprising:
- a substrate;
- a channel layer on the substrate, wherein the channel layer includes a first transistor structure;
- and
- a capacitor layer including a first capacitor structure, wherein the first capacitor structure is electrically connected to the first transistor structure,
- wherein a first point on the substrate corresponding to the first transistor structure is different from a second point on the substrate corresponding to the first capacitor structure.
A memory device, comprising:
- a memory cell array;
- a plurality of wordlines electrically connected to the memory cell array;
- and
- a plurality of bitlines electrically connected to the memory cell array, wherein:
- the plurality of wordlines include a first wordline,
- the memory cell array includes a first plurality of memory cells electrically connected to the first wordline,
- the first plurality of memory cells respectively include a first plurality of capacitor structures, and
- a capacitor interval for the first plurality of capacitor structures is greater than a bitline interval for the plurality of bitlines.
(canceled)
Dependencies are inferred from the claim text.