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US 2026/0246453 A1Published application
Accurate Delay generator and Accurate Oscillator
OwnerMilind Chandra Guptainventor
Life of this patent
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Abstract
A delay circuit comprising self calibrating means. The process, supply and temperature dependent error of intrinsic delay of a comparator in a delay circuit is self calibrated out of the generated delay. The intrinsic delay is used to self adjust the delay generating reference to remove effect of the intrinsic delay during delay generation. A relaxation oscillator circuit comprising the delay circuit blocks to create a process, supply and temperature independent oscillation frequency.
Claims13
A method for calibrating a delay generation circuit comprising:
- comparator based delay generator including:
- a comparator to generate a delayed output signal
- wherein said comparator responds to an input after an intrinsic delay TPD which is a process, supply and temperature dependent parameter;
- and
- a first signal ramp produced at a controlled slope to create a predetermined time varying signal, to generate the desired delay, coupled to said comparator first input;
- and
- a predetermined reference signal coupled to said comparator first input;
- and
- a switch to select said reference, in the calibration phase, or said first signal ramp, in the delay phase, to be coupled to said comparator first input;
- and
- a second signal ramp, produced at a negative slope of said first signal ramp, coupled to said comparator second input;
- and
- a signal hold means to hold the signal level of said second signal ramp
- wherein after calibration said hold signal level is substantially in accordance with the following relationship to said reference, said comparator propagation delay TPD, and said first signal ramp slope S:
- HOLD_SIGNAL
- =
- REFERENCE
- -
- T
- PD
-
- S
- a logic circuit to generate the control signals.
20 more elements
An accurate relaxation oscillator circuit comprising:
- two comparator based delay circuits each including:
- a comparator to generate a delayed output signal
- wherein said comparator responds to an input after an intrinsic delay TPD which is a process, supply and temperature dependent parameter;
- a first signal ramp produced at a controlled slope to create a predetermined time varying signal, to generate a portion of the oscillation time period, coupled to said comparator first input;
- and
- a predetermined reference signal coupled to said comparator first input;
- and
- a switch to select said reference, in the calibration phase, or said first signal ramp, in the delay phase, to be coupled to said comparator first input;
- and
- a second signal ramp, produced at a negative slope of said first signal ramp, coupled to said comparator second input;
- and
- a signal hold means to hold the signal level of said second signal ramp
- wherein after calibration said hold signal level is substantially in accordance with the following relationship to said reference, said comparator propagation delay TPD and said first signal ramp slope S:
- HOLD_SIGNAL
- =
- REFERENCE
- -
- T
- PD
-
- S
- a logic circuit that takes the output of said two delay circuits and generates the right logic signals for controlling the timing and calibration of each of the delay circuits.
19 more elements
Dependencies are inferred from the claim text.