Analog front end with compensated open loop stage

A method of operating an analog front-end circuit, the method comprising:

• generating a differential voltage across control terminals of a first differential transistor pair by flowing a first current through a reference resistor;
• steering a second current through the first differential transistor pair based on the differential voltage;
• mirroring the second current through first and second current mirrors;
• scaling the mirrored second current by a factor k through a third current mirror;
• providing the scaled second current to a current sink coupled to a second differential transistor pair, wherein the second differential transistor pair has transistors with width-to-length ratios k times larger than transistors in the first differential transistor pair;
• receiving differential input signals at control terminals of the second differential transistor pair;
• and
• generating differential output voltages across load resistors coupled to outputs of the second differential transistor pair, wherein the load resistors match a resistor type of the reference resistor.

An analog front-end circuit, comprising:

• an open-loop gain stage including:
• a first and second complementary transistor pairs configured as inverters,
• first and second resistors coupled to set DC operating points for the inverters, and
• first and second RC networks coupled to provide AC coupling for differential input signals;
• and
• a closed-loop stage including:
• a differential transistor pair having transistors with width-to-length ratios scaled by a factor 1/k relative to transistors in the first and second complementary transistor pairs,
• a reference resistor coupled to receive a first current to generate a differential voltage,
• first and second current mirrors coupled to steer a second current through the differential transistor pair based on the differential voltage,
• third and fourth complementary transistor pairs biased at ground plus a base-to-emitter voltage, and
• a third current mirror configured to scale the second current by the factor k to generate bias currents for the first and second complementary transistor pairs.