Esd and overvoltage clamp

A method comprising:

• providing a signal IC terminal of an integrated circuit;
• providing a clamp of the integrated circuit, the clamp including a first current terminal coupled to the signal IC terminal via a first current path and a second current terminal coupled to a first supply voltage rail of the integrated circuit via a second current path;
• providing a resistive circuit of the integrated circuit located in the first current path between the signal IC terminal and the first current terminal and configured to provide a resistance to the first current path;
• wherein a control terminal of the clamp is coupled to a voltage node of the integrated circuit, wherein when a voltage of the first current terminal of the clamp is higher by at least a first amount above a voltage of the control terminal of the clamp, the clamp becomes conductive to make conductive a discharge path between the signal IC terminal and the first supply voltage rail to reduce a voltage of the signal IC terminal with respect to a voltage of the voltage node, wherein the discharge path between the signal IC terminal and the first supply voltage rail is through the resistive circuit and is through the clamp;
• providing a first transistor of the integrated circuit including a first current terminal coupled to the control terminal of the clamp, a second current terminal coupled to the first supply voltage rail, and a control terminal configured to receive an ESD trigger signal whose assertion is indicative of a detected ESD event, wherein in response to an assertion of the ESD trigger signal, the first transistor is made conductive to pull a voltage of the control terminal of the clamp towards a voltage of the first supply voltage rail to make the clamp conductive to make conductive the discharge path between the signal IC terminal and the first supply voltage rail for discharging ESD current.

An integrated circuit (IC) comprising:

• a signal IC terminal;
• a PFET including a source coupled to the signal IC terminal via a first current path and a drain coupled to a first supply voltage rail via a second current path;
• a resistive circuit located in the first current path between the signal IC terminal and the source and configured to provide a resistance to the first current path;
• wherein a gate of the PFET is coupled to a second supply voltage rail, wherein when a voltage of the source is higher by at least a first amount above a voltage of the gate, the PFET becomes conductive to make conductive a discharge path between the signal IC terminal and the first supply voltage rail to reduce a voltage of the signal IC terminal with respect to a voltage of the second supply voltage rail, wherein the discharge path between the signal IC terminal and the first supply voltage rail is through the resistive circuit and is through the PFET;
• an NFET including a drain coupled to the gate of the PFET, a source coupled to the first supply voltage rail, and a gate configured to receive an ESD trigger signal whose assertion is indicative of a detected ESD event, wherein in response to an assertion of the ESD trigger signal, the NFET is made conductive to pull a voltage of the gate of the PFET towards a voltage of the first supply voltage rail to make the PFET conductive the discharge path between the signal IC terminal and the first supply voltage rail for discharging ESD current.