US 2026/0246262 A1 · Overcurrent Protection for Bidirectional Power Semiconductor Devices

Abstract

Overcurrent protection for bidirectional power semiconductor devices. At least one example is a method of operating a switch assembly, the method comprising: conducting a forward load current from an upper terminal of the switch assembly, then through a power semiconductor device, then through a lower cascode FET, and then through a lower terminal of the switch assembly; and simultaneously driving a forward sense current from a lower gate driver through the power semiconductor device; and thereafter interrupting, by the lower gate driver, the forward load current by de-asserting a gate of the lower cascode FET, the interrupting responsive to a voltage used to drive the forward sense current exceeding a predetermined threshold; and interrupting, by the lower gate driver, a reverse sense pathway of an upper gate driver.

Claims19

Dependent claims

A method of operating a switch assembly, the method comprising:

conducting a forward load current from an upper terminal of the switch assembly, then through a power semiconductor device, then through a lower cascode FET, and then through a lower terminal of the switch assembly;
and simultaneously
driving a forward sense current from a lower gate driver through the power semiconductor device;
and thereafter
interrupting, by the lower gate driver, the forward load current by de-asserting a gate of the lower cascode FET, the interrupting responsive to a voltage used to drive the forward sense current exceeding a predetermined threshold;
and
interrupting, by the lower gate driver, a reverse sense pathway of an upper gate driver.

4 more elements

A switch assembly comprising:

an upper terminal, a lower terminal, and a control input;
an upper cascode FET defining a first lead coupled to the upper terminal, a second lead, and a gate;
a lower cascode FET defining a first lead coupled to the lower terminal, a second lead, and a gate;
a power semiconductor device coupled between the second leads and having a control lead;
a driver comprising:
an upper transistor defining a first lead coupled to the upper terminal, a second lead, and a base;
a lower transistor defining a first lead coupled to the lower terminal, a second lead, and a base;
an upper gate-driver having a drive-in terminal, a drive terminal coupled to both the gate of the upper-cascode FET and the base of the upper transistor, and a sense terminal coupled to the second lead of the lower transistor, the upper gate-driver is configured to, responsive to assertion of its drive-in terminal, drive a reverse sense current through the lower transistor and the power semiconductor device;
the upper gate-driver configured to, responsive to an overcurrent condition detected using the reverse sense current, de-assert its drive terminal to make the upper-cascode FET and the upper transistor non-conductive;
a lower gate-driver having a drive-in terminal, a drive terminal coupled to both the gate of the lower-cascode FET and the base of the lower transistor, and a sense terminal coupled to the second lead of the lower transistor, the lower gate-driver is configured to, responsive to assertion of its drive-in terminal, drive a forward sense current through the upper transistor and power semiconductor device;
and
the lower gate-driver configured to, responsive to an overcurrent condition detected using the forward sense current, de-assert its drive terminal to make the lower cascode FET and the lower transistor non-conductive.

9 more elements

Dependencies are inferred from the claim text.

Overcurrent Protection for Bidirectional Power Semiconductor Devices

Life of this patent

Overcurrent Protection for Bidirectional Power Semiconductor Devices

Life of this patent

Abstract

Claims19