Current profile balancing for flash memory
AssigneeSilicon Storage Technology, Inc.
InventorsHieu Van TRAN, Kyle MCMARTIN, Hyun Bai KIM, Anh LY, Kha NGUYEN, Hien PHAM
Life of this patent
Estimating the term…
Abstract
In one example, a method comprises precharging at least one input to or output from a memory array to a supply voltage; performing at least one operation by the memory array requiring the precharged at least one input to or output from the memory array to have a voltage lower than the supply voltage; and discharging the precharged at least one input to or output from the memory array to the voltage lower than the supply voltage in response to the at least one operation.
Claims23
A method comprising:
- precharging at least one input to or output from a memory array to a supply voltage;
- performing at least one operation by the memory array requiring the precharged at least one input to or output from the memory array to have a voltage lower than the supply voltage;
- and
- discharging the precharged at least one input to or output from the memory array to the voltage lower than the supply voltage in response to the at least one operation.
A method comprising:
- performing an operation on a memory array, wherein the operation is performed by:
- sending first signals to a first plurality of inputs to or outputs from the memory array forming a first group, and
- after sending the first signals, sending second signals to a second plurality of inputs to or outputs from the memory array forming a second group different from the first group;
- wherein each of the first signals and second signals are required to complete the operation.
A system comprising:
- an array comprising non-volatile memory cells arranged into rows and columns;
- and
- an addressing block to address the rows and columns by a binary address sequence having all addresses differ from adjacent addresses in the sequence by fewer than a maximum number of binary bits in the addresses.
A method comprising:
- comparing, by a first address cluster, a first subset of a plurality of address bits with at least one known bad address of a memory array;
- in response to a true result of the comparing by the first address cluster, comparing, by a second address cluster, a second subset of the plurality of address bits with the at least one known bad address of the memory array;
- in response to a true result of the comparing by the second address cluster, storing incoming data in an address of the memory array other than the at least one known bad address.
A system comprising:
- an array of non-volatile memory cells arranged in rows and columns;
- and
- a cluster comparison circuit comprising a plurality of address clusters each configured to compare a respective subset of address bits against a respective portion of at least one known bad address of the memory array;
- wherein in response to each of the plurality of address clusters returning a true result, the array is configured to address the non-volatile memory cells at an address different from an address indicated by the address bits.
A method comprising:
- performing a staggered precharging of a plurality of data lines for a plurality of memory cells, the staggered precharging comprising:
- precharging a first group of the data lines at a first time, and
- precharging a second group of the data lines at a second time after the first time;
- and
- sensing data stored in the plurality of memory cells having the precharged data lines.
A system comprising:
- an array of non-volatile memory cells arranged in rows and columns;
- a plurality of sensing circuits, wherein each of the columns of memory cells in the array is coupled to one of the plurality of sensing circuits;
- and
- a controller for pre-charging the plurality of sensing circuits in a staggered sequence.
Dependencies are inferred from the claim text.