Write time reduction circuit architecture for rram

A read/write switch for an resistive random-access memory (RRAM) structure, comprising:

• a charge pump having an input node coupled to a low voltage and an output node that continuously generates a high voltage;
• a first transistor coupled in series between the output node of the charge pump and a switch output;
• a second transistor coupled between a source voltage and the switch output;
• and
• a level shifter (LS) having a first LS output coupled to a gate of the first transistor and a second LS output coupled to a gate of the second transistor.

A resistive random-access memory (RRAM) structure, comprising:

• a read/write switch including:
• a charge pump having an output node that generates a charge pump output voltage that is variable;
• a first transistor coupled in series between the output node of the charge pump and a switch output;
• a second transistor coupled between a source voltage and the switch output;
• a level shifter (LS) having an enable input that receives a source voltage during a write operation and 0 volts during a read operation, wherein the LS includes a first LS output coupled to a gate of the first transistor and a second LS output coupled to a gate of the second transistor;
• and
• a high voltage selection switch that provides a highest voltage to the LS selected between the source voltage and the charge pump output voltage.