Atomic Smashing

A method, comprising:

• storing, by a computing system, data values in a first cache, wherein:
• the first cache is at a first level in a memory hierarchy;
• the first cache is shared by first and second system on a chip (SoC) components, wherein the SoC is integrated onto one or more co-packaged semi-conductor dies;
• the memory hierarchy includes a memory and one or more component caches that are further from the memory, in the memory hierarchy, than the first cache;
• and
• receiving, by the computing system, multiple requests to atomically update, according to one or more arithmetic operations, a stored data value in the first cache;
• performing, by the computing system, updates to the stored data value based on the multiple requests, in response to determining that the one or more arithmetic operations meet one or more criteria;
• storing, by the computing system, operation information that indicates a most-recent requested atomic arithmetic operation for the updated data value;
• and
• synchronizing, by the computing system in response to an event, with one or more other caches in the memory hierarchy, based on the updated data value and the operation information.

A non-transitory computer-readable medium having instructions of a hardware description programming language stored thereon that, when processed by a computing system, program the computing system to generate a computer simulation model, wherein the model represents a hardware circuit that includes:

• a system on a chip (SoC) integrated onto one or more co-packaged semi-conductor dies, wherein the SoC includes:
• memory controller circuitry configured to control memory circuitry;
• first and second SoC component circuits;
• first cache circuitry configured to store data values, wherein:
• the first cache circuitry is at a first level in a memory hierarchy;
• the first cache circuitry is shared by the first and second SoC component circuits;
• the memory hierarchy includes the memory circuitry and one or more component caches that are further from the memory circuitry, in the memory hierarchy, than the first cache circuitry;
• and
• control circuitry configured to:
• receive multiple requests to atomically update, according to one or more arithmetic operations, a stored data value in the first cache circuitry;
• perform updates to the stored data value based on the multiple requests, in response to determining that the one or more arithmetic operations meet one or more criteria;
• store operation information that indicates a most-recent requested atomic arithmetic operation for the updated data value;
• and
• in response to an event, synchronize with one or more other caches in the memory hierarchy, based on the updated data value and the operation information.