Sparsity-aware compute-in-memory architecture with selective computation bypass

A method for performing vector-matrix multiplication, comprising:

• storing a plurality of weight values in a weight memory;
• receiving a plurality of activation values in an input register;
• generating zero-weight indicators for the plurality of weight values;
• generating zero-activation indicators for the plurality of activation values;
• multiplying the plurality of activation values by the plurality of weight values using a plurality of multipliers;
• summing products from the plurality of multipliers using at least one adder tree;
• and
• selecting an output based on the zero-weight indicators and the zero-activation indicators.

A multiply-accumulate unit comprising:

• weight storage storing a plurality of weight values;
• a plurality of multipliers coupled to the weight storage, and configured to receive a plurality of activation values;
• an adder coupled to the plurality of multipliers;
• zero detection circuitry configured to generate zero-weight indicators based on the plurality of weight values and zero-activation indicators based on the plurality of activation values;
• and
• selector circuitry coupled to the plurality of multipliers and the adder, the selector circuitry configured to select an output based on the zero-weight indicators and the zero-activation indicators.