Voltage reference circuit
OwnerDominique BERGOGNE, Sebastian GAVIRIA DUQUE +1inventors
InventorsDominique BERGOGNE, Sebastian GAVIRIA DUQUE, Plinio BAU
Life of this patent
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OwnerDominique BERGOGNE, Sebastian GAVIRIA DUQUE +1inventors
InventorsDominique BERGOGNE, Sebastian GAVIRIA DUQUE, Plinio BAU
Estimating the term…
A voltage reference circuit (1000) has a first branch (101) with a first depletion-mode top transistor (M1) connected to a voltage source (Vcc), a first enhancement-mode bottom transistor (M3) connected to the ground, and a dipole (D1) connected between the top transistor and the bottom transistor. A second branch (102) having a second depletion-mode top transistor (M4) is connected to a third depletion-mode transistor (M5), itself connected to a second enhancement-mode bottom transistor (M7) connected to the ground, the first top transistor being connected to the third depletion-mode transistor (M5), the first bottom transistor being connected to the second bottom transistor. The reference voltage (Vref) is provided to the source of the second top transistor.
A voltage reference circuit comprising:
The voltage reference circuit according to claim 4, characterised in that the dipole (D11) comprises three enhancement-mode transistors (M21, M22, M23).
Dependencies are inferred from the claim text.