Semiconductor Package with Integrated Capacitors
AssigneeChipletz, Inc.
InventorsMichael Su, Michael Alfano, Siddharth Ravichandran
Life of this patent
Estimating the term…
Abstract
In one aspect, a capacitor or network of capacitors is/are provided for vertical power delivery in a package where the capacitor(s) is/are embedded in or forms the entirety of the package substrate core. In a second aspect, a plurality of thin-film capacitor structures are provided for implementing vertical power delivery in a package. In a third aspect a method is provided for fabricating hermetically sealed thin-film capacitors.
Claims14
A package comprising:
- a substrate core having a top surface and a bottom surface;
- a capacitor having a top surface and a bottom surface, the capacitor forming at least a portion of the substrate core with the top surface of the capacitor substantially co-planar with the top surface of the substrate core and the bottom surface of the capacitor substantially co-planar with the bottom surface of the substrate core;
- a top redistribution layer formed on the top surface of the substrate core, and adapted to facilitate electrical connection to the top surface of the capacitor;
- a bottom redistribution layer formed on the bottom surface of the substrate core, and adapted to facilitate electrical connection to the bottom surface of the capacitor;
- and
- an electrical connection extending vertically through the capacitor, but electrically isolated from the capacitor.
A package adapted to couple a semiconductor die to external circuitry, the package comprising:
- a substrate core having a top surface and a bottom surface;
- a capacitor having a top surface and a bottom surface, the capacitor forming at least a portion of the substrate core with the top surface of the capacitor substantially co-planar with the top surface of the substrate core and the bottom surface of the capacitor substantially co-planar with the bottom surface of the substrate core;
- a top redistribution layer formed on the top surface of the substrate core, and adapted to facilitate electrical connection to the top surface of the capacitor;
- a bottom redistribution layer formed on the bottom surface of the substrate core, and adapted to facilitate electrical connection to the bottom surface of the capacitor;
- and
- an electrical connection (180, 300) extending vertically through the capacitor, but electrically isolated from the capacitor;
- wherein the capacitor is embedded in the substrate core;
- and
- wherein the package includes fine pitch wiring between different surface attachable devices on the package, and coarser density wiring to connect the surface attachable devices to the external circuitry.
A package adapted to couple a semiconductor die to external circuitry, the package a first level interconnect having a top contact adapted to be coupled to the semiconductor die, and a bottom contact;
- a substrate core comprising a capacitor having a top terminal coupled to the bottom contact of the first level interconnect, and a bottom terminal;
- a redistribution layer having a top contact coupled to the bottom terminal of the capacitor, and a bottom terminal;
- a second level interconnect having a top contact coupled to the bottom terminal of the redistribution layer, and a bottom contact adapted to be coupled to the external circuitry;
- and
- an electrical connection (180, 300) extending vertically through the capacitor, but electrically isolated from the capacitor.
A package adapted to couple a semiconductor die to external circuitry, the package a first level interconnect having a top contact adapted to be coupled to the semiconductor die, and a bottom contact;
- a redistribution layer having a top contact coupled to the bottom contact of the first level interconnect, and a bottom contact;
- a substrate core comprising a capacitor having a top terminal coupled to the bottom contact of the redistribution layer, and a bottom terminal;
- a second level interconnect having a top contact coupled to the bottom terminal of the capacitor, and a bottom contact adapted to be coupled to the external circuitry;
- and
- an electrical connection (180, 300) extending vertically through the capacitor, but electrically isolated from the capacitor.
A package adapted to couple a semiconductor die to external circuitry, the package a first level interconnect having a top contact adapted to be coupled to the semiconductor die, and a bottom contact;
- a first redistribution layer having a top contact coupled to the bottom contact of the first level interconnect, and a bottom contact;
- a substrate core comprising a capacitor having a top terminal coupled to the bottom contact of the first redistribution layer, and a bottom terminal;
- a second redistribution layer having a top contact coupled to the bottom terminal of the capacitor, and a bottom terminal;
- a second level interconnect having a top contact coupled to the bottom terminal of the second redistribution layer, and a bottom contact adapted to be coupled to the external circuitry;
- and
- an electrical connection (180, 300) extending vertically through the capacitor, but electrically isolated from the capacitor.
Dependencies are inferred from the claim text.