Device having pairs of stacked power rail structures surrounding double-row complementary field-effect transistors

A semiconductor device comprising:

• a first and second power rail structure extending in parallel, each comprising a bottom power rail and a top power rail arranged above the bottom power rail;
• a first and second row of complementary field-effect transistor (CFET) devices extending in parallel to the first and second power rail structures;
• a row of local interconnects arranged between and extending in parallel to the first and second row of CFET devices, the first row of CFET devices arranged between the first power rail structure and the row of local interconnects, the second row of CFET devices arranged between the second power rail structure and the row of local interconnects;
• and
• a logic cell comprising
• at least one CFET device of the first row of CFET devices configured to implement a first logic gate, and a first local interconnect of the row of local interconnects configured to interconnect a top and bottom source/drain (S/D) of a first CFET device of the at least one CFET device of the first row of CFET devices;
• and
• at least one CFET device of the second row of CFET devices configured to implement a second logic gate, and a second local interconnect of the row of local interconnects configured to interconnect a top and bottom S/D of a second CFET device of the at least one CFET device of the second row of CFET devices,
• wherein the first logic gate is connected to first input and output pins of the logic cell and the second logic gate is connected to second input and output pins of the logic cell, and
• wherein the first power rail structure is configured to power the first logic gate and the second power rail structure is configured to power the second logic gate.