Semiconductor device and semiconductor memory cell including the same

A semiconductor device, comprising:

• a substrate;
• a gate electrode on the substrate;
• a channel layer between the substrate and the gate electrode;
• a source electrode in contact with a first sidewall of the channel layer;
• a drain electrode in contact with a second sidewall of the channel layer, the second sidewall being opposite to the first sidewall;
• and
• an oxide layer interposed between the gate electrode and the substrate,
• wherein the channel layer includes:
• a first channel pattern in contact with at least one of the source electrode and the drain electrode;
• and
• a second channel pattern between the first channel pattern and the gate electrode,
• wherein the first channel pattern and the second channel pattern include oxide semiconductor materials different from each other,
• wherein the oxide layer includes a protrusion protruding between the source electrode and the drain electrode,
• wherein a top surface of the protrusion is coplanar with a top surface of the source electrode and a top surface of the drain electrode,
• wherein the channel layer is in contact with the top surface of the protrusion.

A semiconductor memory cell, comprising:

• a substrate;
• a semiconductor device on the substrate;
• a landing pad on the semiconductor device;
• and
• a capacitor including bottom electrodes, a top electrode, and a dielectric layer interposed between the bottom electrodes and the top electrode, the capacitor being connected through the landing pad to the semiconductor device,
• wherein the semiconductor device includes:
• a gate electrode on the substrate;
• a channel layer between the substrate and the gate electrode;
• a source electrode in contact with a first sidewall of the channel layer;
• a drain electrode in contact with a second sidewall of the channel layer, the second sidewall being opposite to the first sidewall;
• and
• an oxide layer interposed between the source electrode and the substrate and between the drain electrode and the substrate,
• wherein the channel layer of the semiconductor device includes:
• a first channel pattern in contact with at least one of the source electrode and the drain electrode, the first channel pattern including a crystalline oxide semiconductor material;
• and
• a second channel pattern between the first channel pattern and the gate electrode, the second channel pattern including an amorphous oxide semiconductor material, and
• wherein the gate electrode has a T-shape structure in which at least a portion of the gate electrode is buried in the oxide layer.