US 2026/0239660 A1 · Complementary Depletion Transistor Technology

Abstract

A pair of N and P channel depletion MOFSETs (NDEP and PDEP respectively) are disclosed. Each MOFSET may have a FINFET geometry. The depletion mode MOSFETs may have properties facilitating reduction of the number of transistors in a MOSFET circuits. A two-transistor retention element is disclosed. For example, the gate of an NDEP may be linked (e.g., connected by a conductor) to the gate of a PDEP to form a reverse bias diode. A single transistor pass gate is disclosed. For example, a single PDEP and/or NDEP may be formed into a pass gate. A 2-transistor retention element combined with a single transistor pass gate is disclosed to form a three transistor Static Random Access Memory (SRAM).

Claims21

Dependent claims

An N-channel depletion mode transistor comprising:

a P-doped substrate;
a fin protruding from said P-doped substrate said fin including
a P-doped base layer in contact with the P-doped substrate a N doped channel in contact with the P-doped base;
a gate in proximity to an intermediate location on the N-doped channel and electrically insulated from the N-doped channel;
a source in electrical contact with the N-doped channel on a first side of said intermediate location and a drain in electrical contact with the N-doped channel on a second side of said intermediate location, opposite first side.

2 more elements

Dependencies are inferred from the claim text.

Complementary Depletion Transistor Technology

Life of this patent

Complementary Depletion Transistor Technology

Life of this patent

Abstract

Claims21