Semiconductor memory device

A method of fabricating a semiconductor memory device, comprising:

• preparing a first substrate structure including a cell array region and a peripheral circuit region, the first substrate structure comprising a semiconductor substrate, an insulating layer, and an active layer;
• forming a back-gate electrode in the active layer to extend along a first direction, in the cell array region;
• patterning the active layer to form first and second active patterns on the insulating layer in the cell array region and to form a third active pattern on the insulating layer in the peripheral circuit region, each of the first, second, and third active patterns having a first surface and a second surface opposite to the first surface;
• forming word lines at a side of the first active pattern and at an opposite side of the second active pattern;
• forming bit lines, which are in contact with the first surfaces of the first and second active patterns and are extended along a second direction to cross the word lines;
• bonding a second substrate to the bit lines;
• removing the semiconductor substrate and the insulating layer of the first substrate structure to expose the second surfaces of the first, second, and third active patterns;
• forming a peripheral gate electrode on the second surface of the third active pattern;
• forming a first interlayer insulating pattern to cover the second surfaces of the first and second active patterns, in the cell array region;
• forming a first etch stop layer to cover the first interlayer insulating pattern and the peripheral gate electrode with a uniform thickness;
• and
• forming a second interlayer insulating pattern on the first etch stop layer and in the peripheral circuit region.