Semiconductor device

A semiconductor device comprising:

• a phase detector configured to receive a data signal and N-phase clock signals having phases different from each other, where N is an integer of 2 or more, and output N-bit phase detection data by latching the N-phase clock signals at the edge of the data signal;
• a phase judgement circuit configured to select one of the N phases based on the N-bit phase detection data and output a phase selection signal indicating the phase to be selected;
• a timing adjustment circuit configured to receive the phase selection signal, and output a delayed phase selection signal by delaying the phase selection signal by a delay time determined for each phase to be selected;
• a clock selection circuit configured to receive the N-phase clock signals and select and output a clock signal having a phase selected by the delayed phase selection signal out of the N-phase clock signals, and
• a data latch circuit that latches the data signal with the clock signal that has been selected by the clock selection circuit.