Non-volatile memory and corresponding manufacturing method

A non-volatile memory device comprising:

• a control gate vertically buried in a semiconductor substrate and common to a first memory cell and a second memory cell located on opposite sides of the control gate, each of the first and second memory cells including
• a first conduction region located at a top surface of the substrate at a respective side of the control gate,
• a second conduction region located at depth at a bottom of a trench containing the control gate,
• a vertical implanted region located along the respective side of the control gate in the semiconductor substrate, and
• a dielectric interface to trap electrical charges covering the respective side of the control gate;
• and
• a memory circuit configured to selectively read a bit of a selected one of the first and second memory cells by:
• applying a non-zero read potential to one of the first conduction region and the second conduction region of the selected memory cell,
• applying a reference potential to the other of the first conduction region and the second conduction region of the selected memory cell,
• sweeping a voltage applied to the control gate to detect a threshold voltage of the selected memory cell, and
• maintaining the first conduction region of a non-selected one of the first and second memory cells at a floating potential.