Tensor mapping unit for a hardware integrated circuit

A method for accelerating tensor computations for a machine-learning (ML) model implemented on an integrated circuit that includes a processing engine and a tensor mapping unit, the method comprising:

• generating, by the processing engine, an instruction that is used to compute an output of the ML model,
• wherein the instruction is executable at the integrated circuit to cause performance of operations comprising:
• generating, by the tensor mapping unit, a plurality of tensor element positions for a tensor based on the instruction;
• determining, by the tensor mapping unit, that a first subset of the plurality of tensor element positions is assigned to a first compute tile of the integrated circuit;
• and
• generating, by the tensor mapping unit, control signals to obtain a group of inputs from a tile memory of the first compute tile based on the first subset.