Nonvolatile memory device with memory cell arrays

A nonvolatile memory device comprising:

• a first chip;
• and
• a second chip stacked on the first chip, wherein the first chip comprises
• a first memory cell array comprising a plurality of planes,
• a first page buffer circuit connected to the first memory cell array through a plurality of bit lines,
• a first input/output circuit connected to the first page buffer circuit through a plurality of data lines,
• a first control logic circuit configured to control an operation for the plurality of planes based on a first command,
• a first command-address pad set electrically connected to the first control logic circuit and electrically connected to a first command-address line, and
• a second command-address pad set electrically connected to the first control logic circuit and electrically connected to a second command-address line, wherein the second chip comprises
• a second memory cell array comprising a plurality of planes,
• a second page buffer circuit connected to the second memory cell array through a plurality of bit lines,
• a second input/output circuit connected to the second page buffer circuit through a plurality of data lines,
• a second control logic circuit configured to control an operation for the plurality of planes based on a second command,
• a third command-address pad set electrically connected to the first command-address line, and
• a fourth command-address pad set electrically connected to the second command-address line, wherein a reception duration of the first command through the first command-address line overlaps with a reception duration of the second command through the second command-address line.

A nonvolatile memory device comprising:

• a memory cell array comprising a plurality of planes;
• a page buffer circuit connected to the memory cell array through a plurality of bit lines;
• an input/output circuit connected to the page buffer circuit through a plurality of data lines;
• a control logic circuit configured to control an operation for the plurality of planes based on a command;
• a first command-address pad set electrically connected to the control logic circuit, wherein the first command-address pad set is configured to receive a first command;
• a second command-address pad set electrically connected to the control logic circuit, wherein the second command-address pad set is configured to receive a second command;
• and
• at least one data pad set electrically connected to the input/output circuit, wherein the at least one data pad set is configured to output a first data corresponding to the first command and a second data corresponding to the second command,
• wherein the control logic circuit is configured to determine a plane among the plurality of planes to which the first command-address pad and the second command-address pad sets are allocated based on a data size in a data output operation.