Phase-locked loop circuit, storage device including the phase-locked loop circuit, and operation method of the storage device

A phase-locked loop circuit comprising:

• a phase detector configured to receive a reference clock signal and a feedback clock signal, and output a phase-difference signal corresponding to a phase difference between the reference clock signal and the feedback clock signal;
• a reset synchronization circuit configured to receive a reset signal and the reference clock signal, synchronize the reset signal based on the reference clock signal to generate a synchronous reset signal, and output the synchronous reset signal;
• and
• a frequency divider configured to receive the synchronous reset signal and an output clock signal, reset based on the synchronous reset signal, generate the feedback clock signal by dividing a frequency of the output clock signal, and output the feedback clock signal to the phase detector,
• wherein the phase-locked loop circuit is configured to, based on being powered on, perform a locking operation for locking a phase of the output clock signal, by synchronizing the reset signal based on the reference clock signal.

A phase-locked loop circuit comprising:

• a phase detector configured to receive a reference clock signal and a feedback clock signal, and output a phase-difference signal corresponding to a phase difference between the reference clock signal and the feedback clock signal;
• a voltage generator configured to receive the phase-difference signal, generate an input voltage corresponding to the phase-difference signal, and output the input voltage;
• an oscillator configured to receive the input voltage, generate an output clock signal that has a frequency corresponding to the input voltage, and output the output clock signal;
• a reset synchronization circuit configured to receive a reset signal and the reference clock signal, synchronize the reset signal based on the reference clock signal to generate a synchronous reset signal, and output the synchronous reset signal;
• and
• a frequency divider configured to receive the synchronous reset signal and the output clock signal, reset based on the synchronous reset signal, generate the feedback clock signal by dividing the frequency of the output clock signal, and output the feedback clock signal.