Reconstituted wafer-to-wafer hybrid bonding interconnect architecture with known good dies

An electronic system, comprising:

• a substrate having a top side above a bottom side;
• solder balls beneath the bottom side of the substrate;
• a first die coupled to the top side of the substrate by first interconnects, the first die having through silicon vias (TSVs) therein;
• a second die coupled to the top side of the substrate by second interconnects, the second die having TSVs therein, and the second die laterally spaced apart from the first die;
• an underfill surrounding the first interconnects and the second interconnects;
• a third die over and coupled to the first die;
• a fourth die over and coupled to the first die, the fourth die laterally spaced apart from the third die;
• a fifth die over and coupled to the second die;
• a sixth die over and coupled to the second die, the sixth processor die laterally spaced apart from the fifth die;
• and
• a silicon carrier over the third die and the fourth die.

A method of fabricating an electronic system, the method comprising:

• providing a substrate having a top side above a bottom side;
• forming solder balls beneath the bottom side of the substrate;
• coupling a first base die to the top side of the substrate by first interconnects, the first base die having through silicon vias (TSVs) therein;
• coupling a second base die to the top side of the substrate by second interconnects, the second base die having TSVs therein, and the second base die laterally spaced apart from the first base die;
• forming an underfill surrounding the first interconnects and the second interconnects;
• coupling a first processor die to the first base die;
• coupling a second processor die to the first base die, the second processor die laterally spaced apart from the first processor die;
• coupling a third processor die to the second base die;
• coupling a fourth processor die over to the second base die, the fourth processor die laterally spaced apart from the third processor die;
• and
• providing a silicon carrier over the first processor die and the second processor die.