Chip structure and method of fabricating the same

A chip structure, comprising:

• a die support;
• semiconductor dies disposed on the die support, at least one of the semiconductor dies comprises a semiconductor substrate, an interconnect structure and a first bonding structure, wherein the interconnect structure is connected between the semiconductor substrate and the first bonding structure, the first bonding structure comprises a first bonding dielectric and first bonding conductors embedded in the first bonding dielectric;
• an interconnect bridge extending between the semiconductor dies;
• a dielectric layer beside the interconnect bridge;
• a second bonding structure disposed on the dielectric layer and the interconnect bridge, and comprising a second bonding dielectric in contact with the first bonding dielectric and second bonding conductors in contact with the first bonding conductors, wherein the second bonding dielectric extends laterally beyond the first bonding dielectric to have a sidewall coplanar with the sidewall of the dielectric layer;
• a redistribution circuitry structure disposed on a bottom of the interconnect bridge and a bottom of the dielectric layer, wherein a sidewall of the die support, and a sidewall of the redistribution circuitry structure are coplanar with the sidewall of the dielectric layer.

A chip structure, comprising:

• a bridge structure comprising an interconnect bridge, a dielectric layer laterally surrounding the interconnect bridge and through dielectric vias extending through the dielectric layer, and a first bonding structure disposed on the interconnect bridge and the dielectric layer;
• semiconductor dies disposed on the bridge structure, wherein at least one of the semiconductor dies overlaps both the interconnect bridge and the dielectric layer and comprises a second bonding layer bonded to the first bonding layer;
• a die support covering the semiconductor dies ;
• and
• a dielectric fill disposed between the first bonding layer and the die support and laterally surrounding the semiconductor dies, wherein the dielectric fill is in contact with a sidewall of the second bonding layer and a portion of a top surface of the first bonding layer.