Interconnect substrate and method of making

An interconnect substrate, comprising:

• a substrate core comprising one or more of:
• a dielectric, encapsulant, ceramic, glass, polymer, mold compound, a printed circuit board (PCB), a PCB core, and silicon;
• at least one embedded component disposed in the substrate core, the at least one embedded component comprising one or more of:
• a semiconductor chip, a chiplet, an integrated circuit (IC), a passive device, a vertical interconnect block, an integrated passive device (IPD), a deep trench capacitor (DTC), a transformer, a voltage regulator, a power management IC (PMIC), a filter, a bridge die, and a buffer;
• a first frontside conductive layer disposed over a planarized front surface of the substrate core, the first frontside conductive layer comprising one or more of traces, vias, lands, lines, pads, and planes coupled to the at least one embedded component;
• a first frontside layer of dielectric disposed over the planarized front surface, the at least one embedded component, and the first frontside conductive layer, the first frontside layer of dielectric having a first frontside planar surface exposing at least a portion of the first frontside conductive layer;
• a first backside conductive layer disposed over a back surface of the substrate core, the first backside conductive layer comprising one or more of traces, vias, lands, lines, pads, and planes;
• a first backside layer of dielectric disposed over the back surface of the substrate core, over the at least one embedded component, and over the first backside conductive layer, the first backside layer of dielectric having a first backside planar surface exposing at least a portion of the first backside conductive layer;
• a second backside conductive layer disposed over the first backside planar surface, the second backside conductive layer electrically coupled to the first backside conductive layer;
• and
• a second backside layer of dielectric disposed over the second backside conductive layer and the first backside planar surface, the second backside layer of dielectric having a second backside planar surface exposing at least a portion of the second backside conductive layer.

An interconnect substrate, comprising:

• a substrate core;
• at least one embedded component disposed in the substrate core;
• a first frontside interconnect structure disposed over a front side of the substrate core, the first frontside interconnect structure comprising:
• a first frontside conductive layer coupled to the at least one embedded component,
• a first frontside layer of dielectric disposed over the first frontside conductive layer, the first frontside layer of dielectric having a first frontside planar surface, and
• a second frontside conductive layer disposed over the first frontside planar surface of the first frontside layer of dielectric, the second frontside conductive layer electrically coupled to the first frontside conductive layer;
• a first backside interconnect structure disposed over a back side of the substrate core, the first backside interconnect structure comprising:
• a first backside conductive layer,
• a first backside layer of dielectric disposed over the first backside conductive layer and over the at least one embedded component, the first backside layer of dielectric having a first backside planar surface, and
• a second backside conductive layer disposed over the first backside planar surface, the second backside conductive layer electrically coupled to the first backside conductive layer.