Semiconductor package

A semiconductor package comprising:

• a lower redistribution structure;
• a lower semiconductor chip on the lower redistribution structure, the lower semiconductor chip comprising a lower semiconductor substrate, a lower wiring structure, and a plurality of lower dummy pads, the lower semiconductor substrate comprising an active surface and an inactive surface opposite to the active surface, and the lower wiring structure being on the active surface of the lower semiconductor substrate;
• a plurality of lower dummy wires each having a first end in contact with a corresponding one of the plurality of lower dummy pads of the lower semiconductor chip and a second end opposite to the first end, the second end of each of the plurality of lower dummy wires being spaced apart from the lower redistribution structure and the lower semiconductor chip;
• a lower molding layer on the lower redistribution structure, the lower molding layer being in contact with the lower semiconductor chip and the plurality of lower dummy wires;
• a plurality of lower through vias on the lower redistribution structure, the plurality of lower through vias extending from a lower surface of the lower molding layer to an upper surface of the lower molding layer;
• and
• an upper redistribution structure on the lower molding layer, the upper redistribution structure being electrically connected to the plurality of lower through vias.

A semiconductor package comprising:

• a lower redistribution structure;
• a lower semiconductor chip on the lower redistribution structure, the lower semiconductor chip comprising a lower semiconductor substrate, a lower wiring structure, and a plurality of lower dummy pads, the lower semiconductor substrate comprising an active surface and an inactive surface opposite to the active surface, and the lower wiring structure being on the active surface of the lower semiconductor substrate;
• a plurality of lower dummy wires each having a first end in contact with a corresponding one of the plurality of lower dummy pads of the lower semiconductor chip and a second end opposite to the first end, the second end of each of the plurality of lower dummy wires being spaced apart from the lower redistribution structure and the lower semiconductor chip;
• a lower molding layer on the lower redistribution structure, the lower molding layer being in contact with the lower semiconductor chip and the plurality of lower dummy wires;
• a plurality of lower through vias located on the lower redistribution structure and extending from a lower surface of the lower molding layer to an upper surface thereof;
• an upper redistribution structure on the lower molding layer, the upper redistribution structure being electrically connected to the plurality of lower through vias;
• an upper semiconductor chip on the upper redistribution structure, the upper semiconductor chip comprising an upper semiconductor substrate, an upper wiring structure, and a plurality of upper dummy pads, the upper semiconductor substrate comprising an active surface and an inactive surface opposite to the active surface, and the upper wiring structure on the active surface of the upper semiconductor substrate;
• and
• a plurality of upper dummy wires each having a first end in contact with a corresponding one of the plurality of upper dummy pads and a second end opposite to the first end, the second end of each of the plurality of upper dummy wires being spaced apart from the upper redistribution structure and the upper semiconductor chip.