Variable resistive semiconductor memory device having a barrier layer

Abstract

A semiconductor device including a memory cell is disclosed. The memory cell includes a lower electrode; a variable resistance layer over the lower electrode; an oxygen reservoir layer over the variable resistance layer; and an upper electrode over the oxygen reservoir layer. The variable resistance layer includes a barrier layer; and a switching layer. The barrier layer includes a barrier framework layer having pores; and a barrier sidewall layer conformally formed on sidewalls of the pores of the barrier framework layer. The switching layer is formed over the barrier layer to fill the pores.

Dependencies are inferred from the claim text.