US 2026/0231509 A1 · SEMICONDUCTOR DEVICE FABRICATION WITH INCREASED TRANSISTOR ISOLATION DENSITY

Abstract

Techniques are described for semiconductor device fabrication with increased transistor isolation density by employing a combined cut metal gate (CMG) and epitaxial growth (EPI) patterning (CMGEP) technique to selectively disable transistors in a fabricated array. As described herein, such embodiments provide a larger etching window to avoid EPI damage (i.e., damage to surrounding source/drain structures), and larger margins for avoiding scum defects and photoresist peeling defects. In particular, rather than etching along (in line with) the metal gate line, CMGEP approaches remove a source/drain structure (before or after epitaxial growth) and cut perpendicularly across adjacent metal gate lines in one or more corresponding shallow trench isolation (STI) regions. Techniques are also described for selectively disabling transistors using gate threshold voltage differentiation and/or bottom isolation dielectric deposition.

Claims20

Dependent claims

A method comprising:

forming, on a semiconductor substrate, a plurality of linear channel regions running in parallel to each other in a first direction;
forming a plurality of metal gate lines running in parallel to each other in a second direction orthogonal to the first direction thereby crossing the plurality of linear channel regions;
etching a plurality of source/drain regions each to lie on a respective portion of one of the plurality of linear channel regions and between a respective two adjacent ones of the plurality of metal gate lines;
depositing a respective growth inhibiting layer in each of a selected subset of the source/drain regions, each respective growth inhibiting layer configured to inhibit epitaxial growth;
and
growing an epitaxial layer, such that a source/drain structure grows epitaxially in each of the source/drain regions except for those of the selected subset.

3 more elements

A method for fabricating a semiconductor device comprising:

providing a wafer comprising:
a plurality of linear channel regions running in parallel to each other in an X direction, and formed on a substrate to extend in a positive Z direction from the substrate, the Z direction being orthogonal to the X direction;
and
a plurality of gate lines running in parallel to each other in a Y direction orthogonal to the X and Z directions, the gate lines made of a gate material and disposed on the linear channel regions to form a network of fin arrangements;
etching a plurality of source/drain regions each to lie on a respective portion of one of the plurality of linear channel regions and between a respective two adjacent ones of the plurality of gate lines;
depositing a respective growth inhibiting layer in each of a selected subset of the source/drain regions, each respective growth inhibiting layer configured to inhibit epitaxial growth;
and
growing an epitaxial layer, such that a source/drain structure grows epitaxially in each of the source/drain regions except for those of the selected subset.

5 more elements

Dependencies are inferred from the claim text.

Semiconductor device fabrication with increased transistor isolation density

Life of this patent

Semiconductor device fabrication with increased transistor isolation density

Life of this patent

Abstract

Claims20