Thin film transistor and manufacturing method therefor, and light-emitting substrate

A manufacturing method for a thin film transistor, comprising:

• forming a first gate on a side of a substrate;
• forming an active layer on a side of the substrate away from the first gate, wherein the active layer includes a channel and a first to-be-doped region and a second to-be-doped region that are located on two sides of the channel, and an orthographic projection of the first gate on the substrate at least partially overlaps with an orthographic projection of the second to-be-doped region on the substrate;
• forming a second gate on a side of the active layer away from the substrate;
• performing a conductorization process on the first to-be-doped region and the second to-be-doped region to respectively form a first heavily doped region and a second heavily doped region;
• and
• forming a first electrode and a second electrode on a side of the first gate away from the substrate, wherein the first electrode includes a first via connection portion, the first via connection portion is electrically connected to the first heavily doped region;
• the second electrode includes a second via connection portion, the second via connection portion is electrically connected to the second heavily doped region and the first gate, and an orthographic projection of the second via connection portion on the substrate is located within an orthographic projection of the second heavily doped region on the substrate.

A manufacturing method for a thin film transistor, comprising:

• forming a first gate on a side of a substrate;
• forming an active layer on a side of the substrate away from the first gate, wherein the active layer includes a channel and a first to-be-doped region and a second to-be-doped region that are located on two sides of the channel, an orthographic projection of the first gate on the substrate at least partially overlaps with an orthographic projection of the second to-be-doped region on the substrate, the second to-be-doped region includes a third via connection portion, and the third via connection portion is electrically connected to the first gate;
• forming a second gate on a side of the active layer away from the substrate;
• performing a conductorization process on the first to-be-doped region and the second to-be-doped region to respectively form a first heavily doped region and a second heavily doped region;
• and
• forming a first electrode and a second electrode on a side of the first gate away from the substrate, wherein the first electrode includes a first via connection portion, and the first via connection portion is electrically connected to the first heavily doped region;
• the second electrode includes a second via connection portion, and the second via connection portion is electrically connected to the second heavily doped region;
• an orthographic projection of the second via connection portion on the substrate is within an orthographic projection of the second heavily doped region on the substrate.