US 2026/0231472 A1 · DUAL GATE THIN FILM TRANSISTOR

Abstract

A dual-gate thin film transistor with source, drain, and top gate structures that may be fabricated simultaneously. Each structure includes a conductive semiconductor layer, a gate dielectric layer, and a conductive core. The source and drain structures are made to function as sources and drains by positioning vias to directly contact the conductive semiconductor layer. The top gate structures are made to function as top gate electrodes by positioning vias to contact the conductive cores while avoiding contact with the conductive semiconductor layers. Differences in via width, differences between the widths of the source/drain structures and the width of the top gate structure, or differences in via alignment may be used to achieve conductive semiconductor layer contact for the source/drain structures while avoiding semiconductor layer contact for the top gate structures.

Claims20

Dependent claims

An integrated circuit (IC) device, comprising:

a semiconductor substrate;
a metal interconnect structure disposed over the semiconductor substrate;
a dual-gate thin-film transistor (TFT) comprising:
a channel comprises a first semiconductor layer;
a bottom gate electrode positioned below the channel and separated from the channel by a first gate dielectric layer;
a top gate structure, a source electrode structure, and a drain electrode structure positioned above the channel, each comprising:
a second semiconductor layer;
a conductive core;
and
a second gate dielectric layer disposed between the conductive core and the second semiconductor layer;
a source contact via and a drain contact via, wherein the source contact via and the drain contact via are electrically connected to the second semiconductor layer of the source electrode structure and the drain electrode structure, respectively;
and
a top electrode via electrically connected to the conductive core of the top gate structure.

10 more elements

An integrated circuit (IC) device, comprising:

a semiconductor substrate;
a metal interconnect structure disposed over the semiconductor substrate;
a dual-gate thin-film transistor (TFT) integrated within the metal interconnect structure, the dual-gate TFT comprising:
a first gate structure positioned below a semiconductor channel, the first gate structure including a bottom gate electrode and a first gate dielectric layer separating the bottom gate electrode from the semiconductor channel;
a second gate structure positioned above the semiconductor channel, the second gate structure including a conductive core, a second semiconductor layer, and a second gate dielectric layer disposed between the conductive core and the second semiconductor layer;
a source electrode structure and a drain electrode structure positioned above the semiconductor channel, each including a second semiconductor layer and a conductive core;
a source contact via and a drain contact via, each electrically connected to the second semiconductor layer of the source electrode structure and the drain electrode structure, respectively;
and
a gate contact via electrically connected to the conductive core of the second gate structure.

6 more elements

A method of manufacturing an integrated circuit (IC) device, the method comprising:

forming a bottom gate electrode within a first dielectric layer disposed over a semiconductor substrate;
forming a first gate dielectric layer and a first semiconductor layer over the bottom gate electrode;
patterning the first semiconductor layer to define a channel positioned over the bottom gate electrode, wherein the first gate dielectric layer is interposed between the channel and the bottom gate electrode;
forming a second inter-layer dielectric layer over the channel;
patterning a first opening and two second openings through the second inter-layer dielectric layer, wherein the channel is exposed through the first opening and the two second openings;
depositing a second semiconductor layer, a second gate dielectric layer, and a conductive layer to line and fill the first opening and the two second openings;
planarizing the deposited layers to remove portions of the second semiconductor layer, the second gate dielectric layer, and the conductive layer outside the first opening and the two second openings, such that:
the second semiconductor layer, the second gate dielectric layer, and the conductive layer within the first opening form a top gate structure, and
the second semiconductor layer, the second gate dielectric layer, and the conductive layer within the two second openings form source and drain structures;
forming a third inter-layer dielectric layer over the top gate structure and the source and drain structures;
and
forming a top electrode via and source and drain contact vias through the third inter-layer dielectric layer, wherein:
the top electrode via lands on the conductive layer within the top gate structure and is offset from the second semiconductor layer within the top gate structure, and
the source and drain contact vias land on the second semiconductor layer within the source and drain structures.

11 more elements

Dependencies are inferred from the claim text.

Dual gate thin film transistor

Life of this patent

Dual gate thin film transistor

Life of this patent

Abstract

Claims20