Semiconductor memory device

A semiconductor memory device comprising:

• a first cell structure comprising (i) a first local bitline extending in a vertical direction on a first insulating layer, (ii) a plurality of first cell semiconductor patterns arranged in the vertical direction, each first cell semiconductor pattern having a first end connected to the first local bitline, (iii) a plurality of first data storage devices connected to second ends of the plurality of first cell semiconductor patterns, (iv) a plurality of first cell gate electrodes on the plurality of first cell semiconductor patterns, (v) a first logic semiconductor pattern spaced apart in the vertical direction from the plurality of first cell semiconductor patterns, (vi) a first logic transistor on the first logic semiconductor pattern and connected to the first local bitline, and (vii) a first global bitline connected to the first logic transistor;
• a second cell structure comprising (i) a second local bitline extending in the vertical direction on a second insulating layer, (ii) a plurality of second cell semiconductor patterns arranged in the vertical direction, each second cell semiconductor pattern having a first end connected to the second local bitline, (iii) a plurality of second data storage devices connected to second ends of the plurality of second cell semiconductor patterns, (iv) a plurality of second cell gate electrodes on the second cell semiconductor patterns, (v) a second logic semiconductor pattern spaced apart in the vertical direction from the plurality of second cell semiconductor patterns, (vi) a second logic transistor on the second logic semiconductor pattern and connected to the second local bitline, and (vii) a second global bitline connected to the second logic transistor;
• a bitline contact extending into the second cell structure and connected to the first global bitline and the second global bitline;
• and
• a peripheral circuit structure comprising a peripheral circuit substrate and a peripheral circuit transistor on the peripheral circuit substrate, the peripheral circuit transistor being connected to the first global bitline and the second global bitline.

A semiconductor memory device comprising:

• a first cell structure comprising (i) a plurality of first local bitlines extending in a vertical direction, (ii) a plurality of first memory cells arranged in the vertical direction and connected to the plurality of first local bitlines, respectively, (iii) a plurality of first global bitlines on the plurality of first memory cells, (iv) a plurality of first local bitline multiplexers connected to the plurality of first global bitlines and the plurality of first local bitlines, respectively, and (v) a plurality of first global bitline multiplexers connected to the plurality of first global bitlines, respectively;
• a second cell structure comprising (i) a plurality of second local bitlines extending in the vertical direction, (ii) a plurality of second memory cells arranged in the vertical direction and connected to the plurality of second local bitlines, respectively, (iii) a plurality of second global bitlines on the second memory cells, (iv) a plurality of second local bitline multiplexers connected to the plurality of second global bitlines and the plurality of second local bitlines, respectively, and (v) a plurality of second global bitline multiplexers connected to the plurality of the second global bitlines, respectively;
• and
• a peripheral circuit structure on the second cell structure and comprising a sense amplifier connected to the plurality of first global bitlines and the plurality of second global bitlines.