Semiconductor device having resistive voltage divider

An apparatus comprising:

• a resistor pattern having a first end supplied with a first power potential, a second end supplied with a second power potential different from the first power potential, and first and second nodes positioned between the first end and the second end;
• a plurality of transistors each having a first diffusion region and a second diffusion region;
• and
• an output power line coupled in common to the second diffusion regions of the plurality of transistors,
• wherein the resistor pattern is on a first wiring layer,
• wherein the plurality of transistor include a first transistor and a second transistor,
• wherein the first diffusion region of the first transistor is coupled to the first node of the resistor pattern,
• wherein the first diffusion region of the second transistor is coupled to the second node of the resistor pattern, and
• wherein the first node and the second node are coupled via a first section of the resistor pattern without routing through an upper wiring on any one of a plurality of upper wiring layers physically located above the first wiring layer.

An apparatus comprising:

• a plurality of first transistors arranged in a first direction;
• a plurality of second transistors arranged in the first direction;
• a meander-shaped resistor pattern;
• and
• an output power line,
• wherein the plurality of first transistors and the plurality of second transistors are arranged in a second direction perpendicular to the first direction,
• wherein each of the plurality of first and second transistors includes a first diffusion region and a second diffusion region,
• wherein the resistor pattern includes a plurality of first sections extending in the first direction, a plurality of second sections extending in the first direction, and a plurality of third sections extending in the second direction,
• wherein each of the plurality of first sections of the resistor pattern overlaps with and coupled to the first diffusion region of an associated one of the plurality of first transistors,
• wherein each of the plurality of second sections of the resistor pattern overlaps with and coupled to the first diffusion region of an associated one of the plurality of second transistors,
• wherein each of the plurality of third sections of the resistor pattern is coupled between one end of an associated one of the plurality of first sections and one end of an associated one of the plurality of second sections, and
• wherein the second diffusion region of the plurality of first and second transistors are coupled in common to the output power line.