Semiconductor device and memory device

A semiconductor device comprising:

• a first layer comprising an arithmetic processing device and a sense amplifier;
• and
• wherein a second layer comprising a memory device,
• wherein the second layer is provided positioned over the first layer,
• wherein the sense amplifier has is configured to read data from the memory device,
• wherein the memory device comprises a plurality of memory cells,
• wherein the memory cell comprises a first transistor and a second transistor,
• wherein the first transistor comprises a first conductor, a first semiconductor, a first insulator, a second conductor, and a third conductor,
• wherein the first semiconductor comprises a first region positioned on a side surface of a first opening portion,
• wherein the first opening portion penetrates a second insulator and the second conductor,
• wherein the second insulator and the second conductor are positioned over the first conductor,
• wherein the first insulator comprises a second region,
• wherein the second region is in contact with the first semiconductor and covers the first opening portion,
• wherein the third conductor comprises a third region,
• wherein the third region is in contact with the first insulator and covers the first opening portion,
• wherein the second transistor comprises the third conductor, a second semiconductor, a third insulator, a fourth conductor, and a fifth conductor,
• wherein the second semiconductor comprises a fourth region positioned on a side surface of a second opening portion portion,
• wherein the second opening portion penetrates a fourth insulator and the fourth conductor,
• wherein the fourth insulator and the fourth conductor are positioned over the third conductor,
• wherein the third insulator comprises fifth region,
• wherein the fifth region is in contact with the second semiconductor and covers the second opening portion,
• wherein the fifth conductor comprises sixth region,
• wherein the sixth region is in contact with the third insulator and covers the second opening portion, and
• wherein the second opening portion is positioned obliquely above the first opening portion.

A semiconductor device,

• a first layer comprising a sense amplifier;
• and
• a second layer comprising a memory device electrically connected to the sense amplifier,
• wherein the second layer is positioned over the first layer,
• wherein the memory device comprises a plurality of memory cells,
• wherein the memory cell comprises a first transistor and a second transistor,
• wherein the first transistor and the second transistor are electrically connected to each other through a conductor,
• wherein the first transistor comprises a channel formation region in a first semiconductor positioned along a side surface of a first opening portion included in a first insulator,
• wherein the second transistor comprises a channel formation region in a second semiconductor positioned along a side surface of a second opening portion included in a second insulator,
• wherein the second insulator is positioned over the first insulator, and
• wherein the second opening portion comprises a region not overlapping with the first opening portion.