Methods and systems for providing programmable delay for skew adjustment and synchronization

A device comprising:

• a controller configured to provide control signals;
• a phase-lock loop (PLL) coupled to a first clock generator, the PLL being configured to generate a first clock signal, the first clock signal operating at a first frequency;
• a first clock generator configured to generate signal pairs for a plurality of lanes using the first clock signal, a first signal pair being characterized by a second frequency, the second frequency of the same as the first frequency;
• a phase interpolator being configured to generate a second clock signal based on the signal pairs and the control signals;
• a divider configured to generate divided clock signals;
• a first multiplexer coupled to the divider, the first multiplexer being configured to provide a first data stream using an input data stream and the divided clock signals;
• and
• a second multiplexer coupled to the phase interpolator and configured to provide a second data stream using the first data stream and the second clock signal.

A device comprising:

• a controller configured to provide control signals;
• a phase-locked loop (PLL) configured to generate a first clock signal, the first clock signal operating at a first frequency;
• a quadrature clock generator coupled to the PLL, the quadrature clock generator being configured to generate signal pairs;
• a dual-phase interpolator configured to receive the signal pairs and the control signals, the dual-phase interpolator being configured to generate phase-adjusted clock signals for the lane in which it is located;
• a divider coupled to the dual-phase interpolator, the divider being configured to generate divided clock signals using the phase-adjusted clock signals;
• a first multiplexer coupled to the divider, the first multiplexer being configured to provide a first data stream using an input data stream and the divided clock signals;
• and
• a second multiplexer coupled to the phase interpolator and configured to provide a second data stream using the first data stream and the phase-adjusted clock signals.