Low Propagation Delay Voltage Level Translator Circuit

A circuit, comprising:

• a first transistor having a first terminal coupled to a first power supply terminal, a second terminal coupled to an output terminal of the circuit, and a control terminal;
• a second transistor having a first terminal coupled to a second power supply terminal, a second terminal coupled to the output terminal of the circuit, and a control terminal;
• a level shifter having an input coupled to an input terminal of the circuit, an output, a first bias terminal coupled to the first power supply terminal, a second bias terminal coupled to the second power supply terminal, and a third bias terminal coupled to a reference voltage terminal;
• a first plurality of buffers having an input coupled to the output of the level shifter and an output coupled to the control terminal of the first transistor, each of the first plurality of buffers having a first bias terminal coupled to the first power supply terminal and a second bias terminal coupled to the reference voltage terminal;
• and
• a second plurality of buffers having an input coupled to the input terminal of the circuit and an output coupled to the control terminal of the second transistor, each of the second plurality of buffers having a first bias terminal coupled to a third power supply terminal and a second bias terminal coupled to the second power supply terminal.

A voltage level translator, comprising:

• an input buffer having an input terminal, and having an output;
• digital logic having an input coupled to the output of the input buffer, an output, a first bias terminal coupled to a first power supply terminal, and a second bias terminal coupled to a second power supply terminal;
• a level shifter having an input coupled to the output of the digital logic, and having an output;
• and
• an output buffer comprising:
• a first transistor having a first terminal coupled to a third power supply terminal, a second terminal coupled to the output terminal, and a control terminal;
• a second transistor having a first terminal coupled to the second power supply terminal, a second terminal coupled to the output terminal, and a control terminal;
• a first plurality of buffers having an input coupled to the output of the level shifter and an output coupled to the control terminal of the first transistor, each of the first plurality of buffers having a first bias terminal coupled to the third power supply terminal and a second bias terminal coupled to the second power supply terminal;
• and
• a second plurality of buffers having an input coupled to the output of the digital logic and an output coupled to the control terminal of the second transistor, each of the second plurality of buffers having a first bias terminal coupled to the first power supply terminal and a second bias terminal coupled to the second power supply terminal;
• and
• a boost circuit, having a plurality of inputs, each coupled to an output of one of the second plurality of inverters, and having a plurality of outputs, each coupled to an output of one of the first plurality of inverters.

A circuit, comprising:

• a level shifter having an input coupled to an input terminal of the circuit, and an output;
• a first plurality of buffers having an input coupled to the output of the level shifter, and having an output, each of the first plurality of buffers having a first bias terminal coupled to a first power supply terminal and a second bias terminal coupled to a reference voltage terminal;
• and
• a second plurality of buffers having an input coupled to the input terminal of the circuit, and having an output, each of the second plurality of buffers having a first bias terminal coupled to a second power supply terminal and a second bias terminal coupled to a third power supply terminal;
• a first transistor having a first terminal coupled to the first power supply terminal, a second terminal coupled to an output terminal of the circuit, and a control terminal coupled to the output of the first plurality of buffers;
• and
• a second transistor having a first terminal coupled to the third power supply terminal, a second terminal coupled to the output terminal of the circuit, and a control terminal coupled to the output of the second plurality of buffers;
• wherein the level shifter is configured to output a shifted signal responsive to an input signal received at the input terminal, the received input signal having a voltage swing between a voltage at the second power supply terminal and a voltage at the third power supply terminal, and the shifted signal having a voltage swing between a voltage at the first power supply terminal and a voltage at the reference voltage terminal;
• and wherein the voltage at the first power supply terminal is higher than the voltage at the second power supply terminal.