US 2026/0229283 A1 · STATIC RANDOM ACCESS MEMORY DEVICE

Abstract

A static random access memory device includes at least one word line, a first bit line, a second bit line, a power supply line, a first ground line, a second ground line, and a static random access memory cell. The power supply line is parallel to the first bit line, the second bit line, the first ground line, and the second ground line and is perpendicular to the word line. The static random access memory cell includes a first inverter, a second inverter, a first pass transistor, and a second pass transistor. The first inverter and the second inverter are cross-coupled and respectively coupled to the first pass transistor and the second pass transistor. The static random access memory cell is coupled to the power supply line, the first ground line, the second ground line, the word line, the first bit line, and the second bit line.

Claims15

Dependent claims

A static random access memory device comprising:

at least one word line;
a first bit line and a second bit line;
a power supply line;
a first ground line and a second ground line, wherein the power supply line runs in a direction parallel to the first bit line, the second bit line, the first ground line, and the second ground line, and the power supply line runs in a direction perpendicular to the at least one word line;
and
a static random access memory cell including:
a first inverter and a second inverter cross-coupled and coupled to the power supply line, wherein the first inverter is coupled to the first ground line, and the second inverter is coupled to the second ground line;
a first pass transistor coupled to the at least one word line, the first bit line, the power supply line, and the first inverter;
and
a second pass transistor coupled to the at least one word line, the second bit line, the power supply line, and the second inverter.

7 more elements

A static random access memory device comprising:

a plurality of word lines including at least one first word line;
a plurality of bit lines including a first bit line, a second bit line, a third bit line, and a fourth bit line;
a plurality of power supply lines including a first power supply line and a second power supply line;
a plurality of ground lines including a first ground line, a second ground line, a third ground line, and a fourth ground line, wherein the plurality of power supply lines run in a direction parallel to the plurality of bit lines and the plurality of ground lines but perpendicular to the plurality of word lines;
and
a plurality of static random access memory cells including a first static random access memory cell and a second static random access memory cell;
wherein the first static random access memory cell including:
a first inverter and a second inverter cross-coupled and coupled to the first power supply line, wherein the first inverter is coupled to the first ground line, and the second inverter is coupled to the second ground line;
a first pass transistor coupled to the at least one first word line, the first bit line, the first power supply line, and the first inverter;
and
a second pass transistor coupled to the at least one first word line, the second bit line, the first power supply line, and the second inverter;
and
wherein the second static random access memory cell including:
a third inverter and a fourth inverter cross-coupled and coupled to the second power supply line, wherein the third inverter is coupled to the third ground line, and the fourth inverter is coupled to the fourth ground line;
a third pass transistor coupled to the at least one first word line, the third bit line, the second power supply line, and the third inverter;
and
a fourth pass transistor coupled to the at least one first word line, the fourth bit line, the second power supply line, and the fourth inverter.

14 more elements

Dependencies are inferred from the claim text.

Static random access memory device

Life of this patent

Static random access memory device

Life of this patent

Abstract

Claims15